1. Field of the Invention
This invention relates generally to a memory transfer device. More particularly, it relates to a memory transfer device allowing a large number of transfer blocks to be passed over a Peripheral Component Interconnect (PCI) bus in a personal computer.
2. Background of Related Art
In traditional Industry Standard Architecture (ISA) based personal computing systems, a Direct memory Access (DMA) controller is responsible for transferring data between host system memory and peripheral input/output (I/O) devices, e.g., a floppy disk, a hard drive, an audio device, etc.
FIG. 9 shows a conventional personal computer (PC) based system including a host processor 906, and a plurality of peripheral devices 902-904. A DMA controller 910 in communication with a PCI bus 140 through the PCI to ISA bridge 907 facilitates the transfer of blocks of data to and from peripheral to peripheral or host to peripheral.
A conventional DMA controller is typically capable of handling a maximum of only four block transfer channels in a single DMA controller mode. One such conventional DMA controller is a Model 8237 available from Intel and found in many personal computers. In enlarged systems, a secondary DMA controller 912 may be included in a master-slave configuration to the master DMA controller 910 to provide a total of up to 7 data stream transfer channels.
FIG. 10 shows the centrally located input/output (I/O) mapped registers defined for each channel in a DMA controller 910, 912. These registers are typically programmed only by the host 906.
Typical registers in a DMA controller 910, 912 are a 16-bit host buffer address (e.g., source start address) register 940, a destination start address register 942, a 16-bit transfer count (e.g., byte count) register 944, and perhaps even an 8-page buffer (not shown). The conventional DMA controller 910, 912 is programmed with a value of the source start address 940, the destination start address 942, and the length of the data block to be transferred (byte count) 944 for each of the 7 data transfer channels.
To initiate a data transfer, a host device must program each of the source start address 940, the destination start address 942, and the byte count 944, and, whenever the peripheral desires to transfer data, send a request to the DMA controller 910, 912 to initiate the data transfer. To transfer buffered blocks of data relating to a continual data stream, particularly buffered blocks of data having a variable length, the byte count register 944 relating to the appropriate DMA channel must be programmed before the transfer of each block of data. Unfortunately, the time required for communication over the PCI bus 140 to affect the appropriate change in the length of the data block (i.e., to update the byte count register 944) limits the total amount of data which may be transferred in any given amount of time.
Although the centralized concept of a DMA controller provides the ability to transfer as many as 7 data blocks, the transfer requires communication with the centrally located DMA controller 910, 912. Because the conventional DMA controller is centrally located, access may be limiting to certain applications transferring large amounts of data. Moreover, as discussed, applications transferring blocks of data which have a variable length (e.g., some audio applications) require arbitration for the PCI bus 140 and communication with the DMA controller by the requesting device to reset the block length before each data transfer, potentially wasting time, increasing traffic on the PCI bus 140, decreasing efficiency in the data transfer, and expending valuable MIP (million instruction per second) capacity in the requesting device. Thus, management of the data buffer to be transferred is quite limited and does not offer much flexibility to the user in a DMA controller-based system.
Many conventional agents such as an IDE hard disk controller or a SCSI controller have been implemented to use one or two channels of a DMA controller. However, today's computing advances are becoming limited by the relatively small number of block transfer channels made available by conventional DMA controllers. For instance, hardware accelerated multimedia applications would benefit greatly from the ability to transfer more than 7 channels (i.e., data streams) between host memory and peripherals available using today's technology.
There is thus a need for a more versatile and distributed apparatus and method for allowing the transfer of more than 7 data streams in a personal computer (PC) related application.